This invention relates generally to semiconductor devices and, more particularly, to a method for fabricating Metal-Semiconductor-Field-Effect-Transistors (MESFETs).
MESFETs, for example, GaAs MESFETs, also referred to as Schottky-gate field-effect transistors (FETs), may be used in a variety of different electronic applications. These applications range from providing switching operations (e.g., high-speed digital switching) to providing signal amplification. Further, these applications encompass commercial, industrial and military uses.
MESFETs are often included in devices for use in microwave frequency communications and radar. These devices, as well as other devices and systems using or incorporating MESFETs have continually increasing power requirements. For example, the desired power output per MESFET device, such as, per transistor surface area continually increases. The power output of transistors also has improved such that a single transistor can provide more power, thereby allowing the use of a reduced number of transistors for a particular application. The use of a reduced number of transistors results in reduced cost, as well as reduced size and weight for a device incorporating transistors. Thus, fewer MESFET may be used, for example, in high power applications.
Known GaAs MESFETs use a metal electrode in direct contact with a doped GaAs channel region to form a Schottky gate junction. A voltage applied to the gate electrode or junction influences the channel carrier density in the vicinity of the gate electrode such that current flows from a drain to a source through the channel region. Essentially, a Schottky barrier is provided as the gate electrode rather than a semiconductor junction. The drain-to-source voltage can be modulated by varying the voltage applied between the gate electrode and one of the other electrodes of the MESFET. Accordingly, switching operation or amplification can be provided using MESFETs.
In operation, the instantaneous source-to-drain voltage of MESFETs may transition from a relatively high value (approximately twice the drain supply voltage) to a small value, with the associated instantaneous drain-to-source current transitioning in the opposite direction. The maximum allowed drain-to-source voltage must be limited so as to not exceed the breakdown voltage of the transistor. The breakdown voltage is generally determined by the structural parameters of the transistor, which may include, for example, the spacing between the gate electrode and the drain electrode, the breakdown field of the substrate material (e.g., germanium, silicon, gallium arsenide, diamond, etc.), the doping levels of the various regions, the dimensions of the doped regions, and the configuration or shape of the gate electrode and adjoining material. Further, the breakdown field of a material is related to the band gap of the material. Thus, materials with larger band gaps can be used to form transistors with higher breakdown voltages.
It is know to manufacture planar MESFETs having improved open channel burnout characteristics by adding a burnout improvement region at the drain contact. The process for manufacturing these planar MESFETs typically includes several implantation steps, for example, first implanting the main FET channel, then providing a coincident deep p-type co-implant that is implanted deeper than the main channel n-type implant. Additionally, a high dose contact implant is then provided that forms a low resistance path to an ohmic drain/source contact. Finally, a burnout improvement (BII) implant is provided and operates as a compensating implant to prevent a p-n+ junction from forming in the drain region of the MESFET channel. Without the BII, there is a strong n+p type reverse biased junction in the drain contact. When the MESFET channel begins to draw current controlled by the gate Schottky, the n+p junction can breakdown by avalanche ionization and cause open channel burnout at low drain voltages. The BII thereby provides a higher breakdown/burnout voltage.
However, it is very difficult to precisely control the n-type BII implant dose and energy in known MESFETs and methods of fabricating MESFETS. In particular, it is difficult to properly and adequately compensate the p-type doping in a small confined region near the drain contact. For example, it is difficult to control the width of the BII region formed by photomask techniques and also to control the dose and energy of the BII implant necessary to repeatedly compensate for the p-type co-implant. The BII implant must be carefully formed, adjusted and controlled to properly compensate for the p-type co-implant. Thus, it is difficult to control the fabrication of the BII of the MESFET. This results in increased variability of and overall reduction in the robustness, for example, the operating range, of the MESFET. Further, these known methods for forming the BII region require an extra processing step through, for example, an ion implanter, which can add time and cost to the process.